1. Field of the Invention
The present invention relates to a priority encoder and a data processor comprising the same. More particularly, it relates to a priority encoder which, when an instruction for transferring a plurality of register contents is executed, encodes two or more register addresses, to which the contents are to be transferred, from a register list, and a data processor capable of transferring the two or more register contents simultaneously by comprising the same.
2. Description of the Related Art
Conventionally, in a data processor, for the purpose of accessing data used frequently at a high speed with a simple mechanism, a register file comprising about 16 general purpose registers is provided and the data being accessed frequently and the intermediate operation results are held in the register file.
In softwares using such register file, a technique for permuting data in the register file at borders of a series of processings is employed. Accordingly, processing for storing the data from the registers to a memory by several numbers continuously at a time, or processings for loading the data from the memory to the registers by several numbers continuously at a time are repeated frequently.
In high-level languages such as the C or the Pascal, a technique of rearranging frequently used variables into the registers at every procedure is used often. Accordingly, in the softwares designed in these high-level languages, it is often the case that a plurality of data are stored to the memory from the registers, or conversely, a plurality of data are loaded to the registers from the memory.
Therefore, a data processor having a multi-data transfer instruction which stores a plurality of data into the memory from the registers by one instruction, or loads a plurality of data to the registers from the memory by one instruction has been proposed hitherto. In such a multi-data transfer instruction, a technique of indicating the register, to which data is to be transferred, by a register list corresponding to a bit string of "0" and "1" is used. Accordingly, it is necessary to search the register list and encode a register number to be transferred at a high speed, therefore, for this purpose an encoding circuit called a priority encoder is proposed as a hardware.
A technique of encoding the register number to be transferred from the register list at a high speed by using the priority encoder is, particularly, disclosed in, for example, U.S. Pat. No. 4,348,741.
In a conventional data processor comprising a priority encoder, when the register list is searched by using the priority encoder to encode a bit position of "1" ( or "0") as binary digits, since it was not clear whether a bit adjacent to the encoded bit position of "1" (or "0") is "1" (or "0"), processings for encoding a position of "1" (or "0") to transfer one data of the register corresponding to the resulting resister number are executed successively. Accordingly, the transferring operation must be repeated, at least, the same frequency as the number of data to be transferred.